A Novel Litho-Litho-Etch Process to Realize Multi-Function SOC Chip Design

Litho-Etch-Litho-Etch (LELE) process and its variance have been widely used in IC industry from 32 nm node and beyond. A pattern solidification step must be performed either by etching into hard mask or by resist freezing after the first exposure in LELE and Litho-Freezing-Litho-Etch (LFLE) processes respectively. One step further, a new resist to enable a Litho-Litho-Etch (LLE) process in which the etching step is removed but still required two times resist processes. In this paper, we describe the use of a simpler LLE process in which two exposure steps are performed on the same resist layer. We demonstrate that the etching bias is significantly improved by the LLE in comparison with that by LELE. Since scanner is used in a non-conventional way during the two exposures, overlay control is also modified accordingly. This new process brings advantages in process simplification as well as cost reduction for production. The exposure is done with ASML NXT1980Di scanner and overlay control uses ASML Litho InSight in combination with fab automation system.