像素
边缘检测
阈值
图像传感器
帧速率
人工智能
帧(网络)
计算机视觉
GSM演进的增强数据速率
CMOS芯片
栏(排版)
计算机科学
图像处理
数学
图像(数学)
算法
工程类
电子工程
电信
作者
Minjun Park,Hyeon‐June Kim
标识
DOI:10.1109/jsen.2023.3263461
摘要
This article presents a real-time edge image extraction CMOS image sensor (CIS) with an edge-detection counter for machine vision applications. By examining a conventional column-parallel (CP) CIS imaging structure with a single-slope analog-to-digital convertor (SS ADC), it discovered an additional time slot available to extract information of an additional image during a normal imaging operation of two adjacent columns. While obtaining a normal image in this study, the prototype CIS with the proposed edge-detection counter effectively utilizes the spare time for extracting an additional column edge image without an image signal processor (ISP) and any computational latency. In addition, by applying a proposed variable edge thresholding function, the proposed CIS can adopt an optimum edge threshold value according to its imaging condition, alleviating an inherent limitation of a column edge image. This prototype CIS was fabricated using a 0.18- $\mu \text{m}$ 1-poly 6-metal (1P6M) CMOS process with an effective pixel resolution of 320 (H) $\times320$ (V). The prototype consumes 17.72-mW power with a frame rate of 240 frames/s. The prototype CIS demonstrated a figure of merit of 721 pW/frame pixel.
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