Room-Temperature Hybrid Bonding of Via-middle TSV Wafer Fabricated by Direct Si/Cu Grinding and Residual Metal Removal

We proposed a via-middle through-silicon via (TSV) wafer stacking process that combined the TSV reveal process comprising direct Si/Cu grinding and residual metal removal treatment with surface-activated bonding using an ultrathin Si film. This detailed process included nine steps: (a) chemical mechanical polishing (CMP) of the frontside surface of the via-middle TSV wafer, (b) edge trimming of the via-middle TSV wafer, (c) bonding of support glass, (d) direct Si/Cu grinding, (e) residual metal removal treatment, (f) deposition of backside insulator, (g) CMP of the backside surface of the via-middle TSV wafer, (h) hybrid bonding (surface-activated bonding using an ultrathin Si film), and (i) debonding of support glass. By applying this process to via-middle TSV wafers (wafer diameter: 200 mm, TSV diameter: 5 μm, TSV depth: 33 μm, and TSV pitch: 20 μm), we confirmed that hybrid bonding was possible at room temperature. In addition, we adjusted the height of Cu protrusion after the CMP step. Consequently, the connection resistance between the TSV and the counter electrode became as low as 100 mΩ without post-bond annealing, and 160000 connections per chip were realized.