Analysis of frequency detection capability of Alexander phase detector

Electronics LettersVolume 56, Issue 4 p. 180-182 Circuits and systemsFree Access Analysis of frequency detection capability of Alexander phase detector Kwanseo Park, Kwanseo Park orcid.org/0000-0002-4727-9868 Department of Electrical and Computer Engineering, Inter-University Semiconductor Research Center, Seoul National University, Seoul, Republic of KoreaSearch for more papers by this authorDeog-Kyoon Jeong, Corresponding Author Deog-Kyoon Jeong dkjeong@snu.ac.kr Department of Electrical and Computer Engineering, Inter-University Semiconductor Research Center, Seoul National University, Seoul, Republic of KoreaSearch for more papers by this author Kwanseo Park, Kwanseo Park orcid.org/0000-0002-4727-9868 Department of Electrical and Computer Engineering, Inter-University Semiconductor Research Center, Seoul National University, Seoul, Republic of KoreaSearch for more papers by this authorDeog-Kyoon Jeong, Corresponding Author Deog-Kyoon Jeong dkjeong@snu.ac.kr Department of Electrical and Computer Engineering, Inter-University Semiconductor Research Center, Seoul National University, Seoul, Republic of KoreaSearch for more papers by this author First published: 01 February 2020 https://doi.org/10.1049/el.2019.3488Citations: 2AboutSectionsPDF ToolsRequest permissionExport citationAdd to favoritesTrack citation ShareShare Give accessShare full text accessShare full-text accessPlease review our Terms and Conditions of Use and check box below to share full-text version of article.I have read and accept the Wiley Online Library Terms and Conditions of UseShareable LinkUse the link below to share a full-text version of this article with your friends and colleagues. Learn more.Copy URL Share a linkShare onFacebookTwitterLinkedInRedditWechat Abstract An analysis of a frequency detection capability of the Alexander phase detector is described. Based on the analysis, a simple modified implementation achieving unilateral frequency acquisition is proposed. The probability of the output occurrence and the frequency detection gain are calculated and verified by simulation. The gain curves show that the proposed phase-frequency detector (PFD) has a unilateral frequency detection capability without a range limitation. The capability is demonstrated through transient simulation of a PLL-based clock and data recovery (CDR) utilising the proposed PFD. The CDR achieves both phase and frequency acquisitions when the initial clock frequency is lower than the data rate. Moreover, the seamless transition from frequency locking to phase locking is obtained. Introduction In general, clock and data recovery (CDR) circuits adopt a dual-loop architecture with a separate frequency detector to achieve phase and frequency acquisitions [1]. However, since the architecture suffers from problems for loop switching and increased power consumption, the recent works obtain both acquisitions using a single-loop architecture with a modified phase detector (PD) [2-5]. Typically, the Hogge PD and the Alexander PD (APD) are the most popular choice in the CDR circuits. While the frequency detection capability of the Hogge PD is analysed in [2], the APD is known to be unable to detect the frequency offset outside the CDR bandwidth. There are several works to resolve the limitation with additional blocks assisting frequency detection [3-5]. However, they suffer from a high power overhead, a long frequency acquisition time, and low compatibility. In [3], frequency detection is achieved by counting the number of consecutive outputs from the APD, but it takes a long time. Unlike the counter-based scheme, fast acquisition is obtained in [4, 5]. However, the approach in [4] requires delay lines for input data dissipating a large power. The multi-phase oversampling scheme proposed in [5] is hard to apply to a sub-rate system. In this work, to mitigate the limitations, the frequency detection capability of the APD is analysed and unilateral frequency acquisition is obtained by one additional logic gate. Alexander phase-frequency detector (APFD) The conventional APD detects a phase difference by using data samples and edge samples. Fig. 1 shows the timing diagrams of the APD operation for three different conditions of the frequency offset. When the clock frequency is same as the data rate and the phase acquisition is done, the rising edges of CK and CKB are aligned to the data centre and the data edge, respectively. However, the phase relationship is not valid if the frequency offset exists. Observing the timing diagrams, in the case of the phase-locked state and the higher clock frequency, there is at most one transition between the two consecutive data samples (D1 and D2). On the other hand, two transitions can exist when the clock frequency is lower than the data rate. That is, UP and DN signals generated by the APD's logic can be high simultaneously. Table 1 shows the occurrence possibility of the UP and DN signals according to the relationship between the clock frequency and the data rate. As we observed, the combination of (1, 1) occurs only when the clock frequency is lower than the data rate. Therefore, unilateral frequency detection is achieved by detecting the combination. Fig 1Open in figure viewerPowerPoint Timing diagrams for different conditions of frequency offset Table 1. Combination of UP and DN signals according to the relationship between clock frequency and data rate (UP, DN) fC = fD, phase locked state fC > fD fC < fD (0, 0) O O O (0, 1) O O O (1, 0) O O O (1, 1) X X O Using the observation, a frequency detection signal can be generated by ANDing the outputs of the APD. To adopt the proposed APFD to a single-loop architecture, its logic is derived by using the direct control of UP/DN paths [5]. As a result, the UP and DN signals of the APFD are expressed as (1) (2) (3)Therefore, the proposed APFD is implemented by a simple modification adding one logic gate to the APD as shown in Fig. 2. While the UP signal of the APFD is same as that of the APD, the DN signal of the APFD is generated by constraining the DN signal of the APD. Fig 2Open in figure viewerPowerPoint Block diagram of proposed APFD Performance of proposed APFD To calculate occurrence probabilities of the APFD's outputs, the logics in (2) and (3) are modified as (4) (5)Assuming that the transition density of the input data equals 0.5, the probabilities can be calculated by using the timing diagram in Fig. 3. The calculation method is to sweep the D1 edge within the unit interval and find the region where the UP or DN signal occurs. Then, the ratio of the region occupied in one period becomes the occurrence probability. Fig. 3 corresponds to the case that the clock frequency is lower than the data rate. The probabilities of the other case and the APD's outputs are also calculated by the same method. Fig 3Open in figure viewerPowerPoint Timing diagram for calculating output probability in APFD a Frequency range of 0.5fD < fC < fD b Frequency range of fC < 0.5fD As a result, the calculated probabilities of generating the UP and DN signals as a function of the clock frequency are shown in Fig. 4. In the APD, the two probabilities are identical in all ranges, resulting in no frequency information. On the other hand, in the APFD, the probability of generating DN is lower than that of generating UP when the clock frequency is lower than the data rate. Using the calculated results, frequency detection curves of the APD and the APFD are plotted as shown in Fig. 5. Unlike the APD, the output of the APFD has a consistent polarity in the case of the negative frequency offset. The simulated frequency detection curves exhibit the same results. Therefore, the proposed APFD has a unilateral frequency detection capability. Fig 4Open in figure viewerPowerPoint Calculated output probability with clock frequency a APD b Proposed APFD Fig 5Open in figure viewerPowerPoint Calculated and simulated frequency detection curves a APD b Proposed APFD In Fig. 6, the frequency acquisition capability of the proposed APFD is verified through the transient simulation. Fig. 6a shows the simulated frequency behaviours of the conventional PLL-based CDR with the APD. The data rate is fixed to 5 Gb/s and various initial frequencies are applied. For the initial frequency near the data rate, frequency acquisition is achieved by the CDR loop bandwidth. However, with a frequency offset outside the loop bandwidth, frequency detection is failed. The simulation results of the PLL-based CDR with the APFD are shown in Fig. 6b. The identical CDR components such as a charge pump, a loop filter, and an oscillator are utilised and the same simulation conditions are applied. As a result, when the initial frequency is lower than the data rate, the CDR with the APFD achieves both phase and frequency acquisitions. In addition to the frequency acquisition capability, the proposed APFD has several advantages. As shown in the transient results, the transition from frequency locking to phase locking is seamlessly achieved without a lock detection signal, thereby avoiding the loop-switching problem. In addition, the frequency acquisition time can be expected because the probabilities of the outputs are clearly known. Furthermore, the proposed APFD can be easily adapted to sub-rate systems for high-speed operation. Fig 6Open in figure viewerPowerPoint Simulated frequency behaviours with various initial frequencies a CDR with APD b CDR with proposed APFD Conclusion This work provides an analysis of the frequency detection capability of the APD and proposes a simple modified structure. The proposed APFD achieves unilateral frequency acquisition without a range limitation or a loop-switching problem. The analysis and the operation are verified by the simulation results. References 1Kocaman, N., Fallahi, S., Kargar, M. et. al.,: 'An 8.5–11.5-Gbps SONET transceiver with referenceless frequency acquisition', IEEE J. Solid-State Circuits, 2013, 48, (8), pp. 1875– 1884 (https://doi/org/10.1109/JSSC.2013.2259033) 2Son, C.H., Byun, S.: 'On frequency detection capability of full-rate linear and binary phase detectors', IEEE Trans. Circuits Syst. II, Express Briefs, 2017, 64, (7), pp. 757– 761 (https://doi/org/10.1109/TCSII.2016.2603522) 3Shu, G., Choi, W.-S., Sexena, S. et. al.,: 'A 4-to-10.5 Gb/s continuous-rate digital clock and data recovery with automatic frequency acquisition', IEEE J. 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