过采样
有效位数
积分器
逐次逼近ADC
功勋
动态范围
电子工程
电气工程
积分ADC
电容器
炸薯条
计算机科学
电压
模数转换器
噪音(视频)
噪声整形
CMOS芯片
工程类
比较器
无杂散动态范围
三角积分调变
物理
光电子学
Ćuk转换器
作者
Yao Li,Yiqiang Q. Zhao,Yifei Zhao,Mao Ye
标识
DOI:10.1016/j.mejo.2021.105292
摘要
This paper proposes a low power fully-passive noise shaping successive approximation register analog-to-digital converter (SAR ADC) for biosensor applications. The proposed ADC includes a second-order fully-passive integrator achieves a second-order noise transfer function. With an independent residue voltage generator to adjust common voltage between the main and residue path, the power efficiency of three differential inputs comparator is improved. The 0.18μm CMOS prototype chip occupies a total area of 1.37 mm2 with a core area of 0.58 mm2 and consumes 131 μW from a 1.3 V supply. The proposed SAR ADC achieves a peak signal-to-noise-and-distortion ratio (SNDR) of 74.8 dB and a peak spurious-free dynamic range (SFDR) of 89.7 dB at a sampling rate of 8 MSPS and oversampling rate of 16, leading to the Schreier figure of merit (FoMs) of the proposed ADC of 167.4 dB.
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