材料科学
铁电性
光电子学
晶体管
非易失性存储器
电气工程
电压
电介质
工程类
作者
Sourav Dutta,Xiaobo Sharon Hu,Khandker Akif Aabrar,Sharadindu Gopal Kirtania,Abhishek Khanna,Kai Ni,Suman Datta
出处
期刊:IEEE Electron Device Letters
[Institute of Electrical and Electronics Engineers]
日期:2022-03-01
卷期号:43 (3): 382-385
被引量:48
标识
DOI:10.1109/led.2022.3148669
摘要
Silicon channel ferroelectric field-effect transistors (FeFETs) with low-k interfacial layer (IL) between ferroelectric and silicon channel suffers from high write voltage, limited write endurance and long read-after-write latency. This is due to early IL breakdown and mobile charge injection at the ferroelectric-IL interface. Here, we demonstrate low voltage, high speed memory operation with high write endurance using an IL-free back-end-of-line (BEOL) compatible FeFET. We fabricated IL-free FeFETs with 28nm channel length (Lg) and 126nm width under a thermal budget < 4000 C by integrating 5nm Hf0.5Zr0.5O2 (HZO) gate stack with amorphous Indium Tungsten Oxide (IWO) semiconductor channel. We report a voltage memory window of 1.6V with a read current window ${I}_{\textit {LVT}}{/}{I}_{\textit {HVT}}$ of 105, write voltage of ±1.6V with 20ns pulses, instantaneous read-after-write latency < 300ns and a record high write endurance exceeding 1011 cycles. This establishes the IL-free BEOL FeFET as a promising candidate for logic-compatible high-performance last-level cache memory.
科研通智能强力驱动
Strongly Powered by AbleSci AI