A Wide Tuning Range Phase Locked Loop for 38 GHz Transceiver in 65 nm CMOS

This paper presents a 4.75 GHz integer N phase locked loop used in combination with frequency multipliers to achieve local oscillator signal for an 8K drone camera 38-GHz transceiver. This PLL achieves a phase noise of -100 dBc/Hz and -103 dBc/Hz at 100 kHz and 1 MHz offset, respectively. The PLL fabricated in 65 nm CMOS technology occupies a die area of 0.21 mm ² . PLL is made programmable to produce accurate LO generation over process, voltage, and temperature variations.