Influence of height difference between chip and substrate on RDL in silicon-based fan-out package

Silicon-based fan-out package is an important Fan-Out Wafer Level Packaging (FOWLP) approach. However, there is usually a height difference between the chip surface and the substrate surface, which influences the reliability of the (redistributed layer) RDL lines connecting the chip and supporting substrate. In this paper, numerical simulation was used to study the von-Mises stress of Re-distributed layer (RDL) under different designs. The influence of dielectric materials, wiring strategies, gap width, chip thickness and other factors on the reliability of the RDL was carefully studied to find out the main influencing factors. The results indicated the gap width was the most important factor to affect the stress of a silicon-based fan-out package. In addition, a test structure was designed and a 5μm wide RDL was successfully prepared to verify the feasibility of the present approach.