40nm Ultra-Low Leakage (40ULL) SRAM - Challenges and Solutions

We present an overview of the 40nm Ultra-Low Leakage (40ULL) SRAMs, aimed at Internet-of-Things (IoT) applications with stringent leakage requirements. We demonstrate SRAM standby leakage (Isb) reduction to ~1.5pA/bit with floating bitlines at 1.1V and a retention leakage 0.4pA/bit achieved through a combination of process technology and design optimizations. The 40ULL technology is qualified with 2000 hours of HTOL stressing with excellent post-stress Vmin characteristics.