Effects of the LPCVD Gate Dielectric Deposition Temperature on GaN MOSFET Channels and the Root Causes at the SiO$_\text{2}$-GaN-Interface

MOSFETs have been fabricated on 150 mm heteroepitaxial gallium nitride (GaN)-on-Si wafers. This work focuses on the significant impact of the gate dielectric deposition temperature and investigates the resulting transistor channel characteristics, the gate dielectric robustness, and the underlying physical mechanisms. It is shown that varying the SiO $_\text{2}$ gate dielectric deposition temperature below and above the GaN decomposition temperature resulted in a channel mobility of 17–55 cm $^\text{2}$ /Vs at threshold voltages of 8.0 to $-$ 3.2 V, respectively. Gate dielectric robustness and reliability studies demonstrated that oxide charging effects and lifetime also depend on the deposition temperature. In addition to the electrical measurements, secondary ion mass spectrometry (SIMS) and transmission electron microscopy (TEM) are used to identify root causes. It is found that various defect types, i.e., chargeable interface states, fixed oxide charges, diffusion of foreign atoms, vacancies, and surface roughness depend on the deposition temperature. In particular, SIMS measurements revealed a temperature-dependent diffusion of potential n-type dopants, originating from the SiO $_\text{2}$ deposition, into the p-type channel region. As further tuning parameter of threshold voltage and channel mobility, the influence of the magnesium doping concentration of the p-body layer is investigated.