Design Analysis of an Energy-Efficient Low-Power Dynamic Comparator Using NMOS Based Preamplifier

Preamplifier stage is an essential module while designing dynamic regenerative comparators for low-voltage and low-power Analog to Digital Converters (ADC) designs. In this paper, a preamplifier stage is designed using NMOS transistors which allows the comparator to have faster comparison speed and lower power dissipation of the circuit. A pass transistor (PMOS) is used in the latch stage for setting the output nodes to a level above of half the supply voltage . The proposed circuit is implemented on both 90nm and 180nm CMOS technology and compared. A supply voltage of 1V is used to power the proposed comparator with a common mode input voltage of 0.9V and modelled using the 90nm CMOS technology Cadence Virtuoso Analogue Design Environment. The proposed comparator is operated at a 1GHz clock frequency and shows a power dissipation of 16.52µW with time delay of 72.09ps. The suggested comparator has 18.14V/nsec slew rate and is found to be energy efficient with 0.297fJ/conversion. The comparator proposed can run up to the highest clock speed of 4GHz. Monte Carlo Analysis for 200 samples is performed to validate the comparator parameters on delay, power consumption and offset voltage.