Low Power Latch Comparator - A Study

With the development of modern VLSI technologies, it is possible to design Biomedical ICs for monitoring systems. These ICs consume more power which causes more noise interference and to overcome these problems, in this paper we studied power efficient and high-speed ADCs, including dynamic latch comparator with low noise interference, low offset voltage, high speed and low power consumption, are designed for long life batteries for these applications. With low offset voltage, the comparator can drive higher loads. In this paper we will discuss various topologies of low power comparators suitable for mixed signal design.