Analog Front End of 50-Gb/s SiGe BiCMOS Opto-Electrical Receiver in 3-D-Integrated Silicon Photonics Technology

This work presents a 3-D-integrated opto-electrical receiver (RX) analog front end (AFE) operating up to 50 Gb/s. The electronic integrated circuit (EIC) is fabricated in ST SiGe BiCMOS-55-nm technology and flipped and mounted on top of the ST photonic integrated circuits (PICs) die through copper pillars (Cu-Pi). In the RX chain, a low-power fully differential shunt-feedback trans-impedance amplifier (FD SF-TIA) is exploited to reduce the input-referred noise. Following the TIA, a postamplifier (PA) based on a novel active feedback circuit topology extends the bandwidth (BW) and a buffer delivers the output electrical signal to the 100- $\Omega $ differential off-chip load. An automatic offset cancellation loop is included to protect the RX from any offset source at the input. The RX AFE consumes 56 mW from 1.8-V supply voltage and provides a trans-impedance (TI) gain of $78.7~\Omega $ with 27-GHz BW. By exploiting the FD SF-TIA with low parasitic capacitance of the germanium photodiodes (Ge-PD) in the photonic die as well as BW recovery by the PA, the RX achieves the sensitivity of −7.5-dBm OMA at Ge-PD and −2.3-dBm OMA at the single-mode fiber (SMF) optical output with bit error rate (BER) of <10 ⁻¹² and PRBS-7. To the author’s best knowledge, among published state-of-the-art 50-Gb/s TIAs and RX exploiting SiGe BiCMOS technologies, this work proves the best energy efficiency ((pJ/bit)) and figure of merit (FoM) ( $({\text {Gbps}}/{\mu \text {A.mW}})$ ) in terms of sensitivity and power consumption.