晶片切割
薄脆饼
材料科学
刀(考古)
模具(集成电路)
机械工程
晶片测试
工程制图
工程类
光电子学
纳米技术
作者
Qiuchen Zhang,Hongbin Xia,Shwu Miin Tan
标识
DOI:10.1109/icept52650.2021.9568214
摘要
Wafer sawing is one of the back-end technologies of advanced packaging. Higher quality and narrower saw street can improve the density of die in one wafer, thus reduce the wafer cost. In this semiconductor industry, there are different wafer dicing methods, blade dicing, laser dicing, stealth dicing and plasma dicing. Plasma dicing gives the best chipping performance, almost zero chipping defect, but it requires high running cost. Laser dicing uses laser ablation to separate units, however, Heat Affect Zone (HAZ) on the sidewall is incurred, which will then lower the die strength. The conventional wafer dicing method, blade dicing, it induces mechanical stress that leads to chipping. The advantage of this technology is mature, low cost comparing with other methods, and it is still the most widely used method in this semiconductor industry. It is believed that with a process optimization, blade dicing is the best option among all. In this paper, we focus on replacing the plasma dicing technology with blade dicing in order to further reduce the processing costs. Result shows: (a) For sidewall chipping, slower feed rate and lower blade height Z1, chipping will be better. (b) For backside chipping, slower spindle speed Z2 and feed rate, lower blade height of Z1, backside reject rate will be decrease. (c) The backside and sidewall chipping size are within the quality specification range through process optimization. (d) All topside chipping are inspected by Automated Optical Inspection (AOI) and meet the standards (>99.8%). (e) Fly die issue can be solved by baking the wafer before sawing.
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