The overlay plays an important role in chip manufacturing for all technology nodes, but controlling it becomes increasingly difficult when the process node is less than 7nm or the number of 3D layers exceeds 100. The primary challenge in overlay control arises from tool and process variation, which can have a significant impact on chip performance and yield. This paper presents a systematic review and analysis based on overlay data and modeling to monitor process and tool variations by exploring and discussing four critical issues related to overlay control: the overlay mark selection method, over-fitting diagnosis method, scanner tool monitoring method, and process grouping method. The selected methods and models can be applied in various areas, including process development, tool monitoring, feedback model selection, and lot grouping.