A Design Methodology for High-Voltage, Highly-Integrated Switched-Capacitor Power Converters, and Implementation At 48 V-12 V, 23 W/cm$^{3}$ and 93.5% Peak Efficiency

In this work, a design methodology and key considerations for high-voltage and highly-integrated switched-capacitor power converters is presented. The design methodology describes the power losses in high-voltage applications, where switching losses and gate-driver losses start becoming dominant compared to fully integrated, low voltage, and low power applications. The design methodology is applicable for any highly-integrated switched-capacitor topology. To verify the design methodology a $\mathbf {48\, }$ – $\mathbf{{12}\;V}$ ladder switched-capacitor power converter in a $\mathbf {180- \, nm}$ SOI BCD process, with external capacitors is implemented. The floating gate-drivers and a clock controller responsible for the power switch control are also presented. The peak efficiency of the proposed power converter is measured to be $\mathbf {93.5 {\%}}$ , and $\mathbf {24.5 \,\;W}$ maximum output power, resulting in a power density of $\mathbf {23 \, \;W}$ /cm $\mathbf {^{3}}$ .