Pushing Low Power Limits on Multi-Core High Performance SoC

The growing popularity of embedded systems in a wide range of applications demand ever greater number of features integrated onto a single SoC to reduce the overall system cost. This high level of integration leads to higher power dissipation, increased thermal system cost, and reduced battery life. To tackle these challenges, SoC should be architected and designed with a holistic view in the context of its usage in the embedded systems. Picking the right knee point of performance and power curve and simplifying operating conditions is the key. This paper presents some novel approaches and techniques developed on a next generation high performance multi-core Sitara MPU device from Texas Instruments.