薄脆饼
德拉姆
弹丸
材料科学
晶圆制造
晶圆规模集成
光电子学
计算机科学
电子工程
工程类
冶金
作者
Kejun Mu,Chuyu Wang,Zhongjie Zhang,Jinyu Tang,Andy Yang,Xiong Li,Jianping Wang,Blacksmith Wu,Kanyu Cao
标识
DOI:10.1109/cecit53797.2021.00104
摘要
As DRAM technology advances combined with more complex process steps than logic, cumulative effect of process variations leads to complicated shot-to-shot or die-to-die distribution in device electrical parameters. In this paper, ion implantation SuperScan by customized wafer dose patterning by shot is introduced to improve the shot-to-shot variability within zone in DRAM process. The wafer level throughput time of ion implantation gets no increase for mass production. The IDS uniformity improvement within zone is up to ∼40%, which then contributes to overall wafer level uniformity improvement (up to ∼30%). Wafer level yield improvement (up to ∼9%) has been verified, which is a major achievement for mass production.
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