模板
平版印刷术
材料科学
电子束光刻
模版印刷
抵抗
蚀刻(微加工)
光学
硅
X射线光刻
图层(电子)
光电子学
投影(关系代数)
临界尺寸
干法蚀刻
纳米技术
计算机科学
物理
算法
计算科学
作者
Isao Amemiya,Hiroshi Yamashita,Sakae Nakatsuka,Tadashi Sakurai,Ikuru Kimura,Mitsuharu Tsukahara,Osamu Nagarekawa
摘要
The development of silicon stencil masks for cell projection lithography (CPL), electron projection lithography (EPL), low-energy electron-beam-proximity-projection lithography (LEEPL), and low-energy electron-beam lithography (LEB) is described. To satisfy the required pattern accuracy of the stencil masks, such as critical dimension and image placement, we developed a high-aspect stencil pattern formation technique to achieve a side-wall angle of over 90 deg and a membrane stress control technique using a stress-correction layer. In addition, for fabricating low-magnification stencil masks, we developed a new mask substrate with a sputtered scattering silicon membrane and a sputtered intermediate stopper layer as an etching stopper. We selected CrNx as the intermediate layer material, which demonstrated high performance in stencil mask fabrication. By improving the CrNx film qualities, its durability to dry and wet etching of backside silicon was improved. In order to improve the pattern image placement accuracy caused by membrane stress changes during stencil pattern formation, we developed a new and simple technique using a stress correction layer, which also functions as a silicon deep-etching mask. By using this functional layer, the total stress change in the pattern field in a mask pattern formation process was reduced to within 5 N/m, which corresponds to less than a 10 nm pattern image placement (IP) error.
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