MOSFET
材料科学
量子隧道
CMOS芯片
光电子学
晶体管
基质(水族馆)
硅
电气工程
场效应晶体管
电压
纳米技术
工程类
海洋学
地质学
作者
Clarissa Convertino,Cezar B. Zota,Heinz Schmid,Daniele Caimi,Lukas Czornomaz,Adrian M. Ionescu,Kirsten E. Moselund
标识
DOI:10.1038/s41928-020-00531-3
摘要
Tunnel field-effect transistors (TFETs) rely on quantum-mechanical tunnelling and, unlike conventional metal–oxide–semiconductor field-effect transistors (MOSFETs), require less than 60 mV of gate voltage swing to induce one order of magnitude variation in the drain current at ambient temperature. III–V heterostructure TFETs are promising for low-power applications, but are outperformed by MOSFETs in terms of speed and energy efficiency when high performance is required at higher drive voltages. Hybrid technologies—combining both TFETs and MOSFETs—could enable low-power and high-performance applications, but require the co-integration of different materials in a scalable complementary metal–oxide–semiconductor (CMOS) platform. Here, we report a scaled III–V hybrid TFET–MOSFET technology on silicon that achieves a minimum subthreshold slope of 42 mV dec−1 for TFET devices and 62 mV dec−1 for MOSFET devices. The InGaAs/GaAsSb TFETs are co-integrated with the InGaAs MOSFETs on the same silicon substrate by means of a CMOS-compatible replacement-metal-gate fabrication flow, allowing independent optimization of both device types. InGaAs/GaAsSb tunnelling field-effect transistors and InGaAs metal–oxide–semiconductor field-effect transistors can be integrated on the same silicon substrate using conventional CMOS-compatible processes, creating a platform for potential use in low-power logic systems.
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