Design of Charge Pump for Low Power, Wide Range PLL in 65nm CMOS Technology

In this paper, a specific circuit topology called NMOS-Switch Current Steering Charge Pump is presented. The circuit is designed using a 65nm CMOS Technology process. The main objective of this design is to minimize the current mismatch between the charging and discharging currents in order to reduce certain undesirable effects such as PLL reference spurs and phase offset. The proposed design employs dual compensation method to address the current mismatch issue. This design was able to achieve a maximum current mismatch of 1.75% compared to the conventional architecture without the dual compensation method had a much higher maximum mismatch of 20%. A current mismatch remained below 1% a range of output voltages from 0.24V to 0.9V, with a supply voltage of 1.2V. A power consumption of the proposed charge pump was measured and found to be 1.48 mW. This power consumption value provides insight into the energy efficiency of the circuit and can be used for further analysis and comparison with other charge pump designs. This design highlights the design and performance characteristics of a specific charge pump topology using a dual compensation method. The experimental results demonstrate the effectiveness of this approach in reducing current mismatch, minimizing PLL reference spurs, and phase offset. The low current mismatch and moderate power consumption make this charge pump design a promising solution for practical applications in various electronic systems.