过采样
电子工程
噪声整形
逐次逼近ADC
转换器
工程类
逆变器
稳健性(进化)
三角积分调变
CMOS芯片
计算机科学
电气工程
电容器
电压
生物化学
化学
基因
作者
A. Badawy,Ayman Ismail
标识
DOI:10.1016/j.mejo.2024.106094
摘要
Noise-Shaping (NS) Successive-Approximation (SAR) Analog-to-Digital Converters (ADCs) are one of the most heavily researched ADC topologies in recent years. This high attention is attributed to the advantages of the NS SAR architecture that combines the merits of ΣΔ and SAR converters. However, the implementation of the NS SAR loop-filter in a passive or an active form imposes challenging tradeoffs among power dissipation, adequacy for scaling with technology, performance, and robustness against process-voltage-temperature (PVT) variations. In this work, a NS SAR ADC realization, based on inverter-based amplification, is proposed that alleviates these design challenges. The proposed implementation is used to design two ADCs in 28 nm CMOS technology to demonstrate its effectiveness. The first ADC employs an active loop-filter and achieves a signal-to-noise-plus-distortion (SNDR) of 62.9 dB, at a sampling frequency of 90 MHz, and an oversampling ratio (OSR) of 4, while consuming 0.59 mW from a 0.9 V supply. The second ADC has a passive loop-filter and provides 61 dB of SNDR for the same OSR and sampling frequency, with 0.58 mW power dissipation.
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