eCIMC: A 603.1-TOPS/W eDRAM-Based Cryogenic In-Memory Computing Accelerator Supporting Boolean/Convolutional Operations

Cryogenic in-memory computing (IMC) presents a promising solution to achieve higher energy efficiency in data-intensive computations at extremely low temperatures. However, existing IMC macros fail to fully exploit the cryogenic device characteristics, such as ultra-low leakage, to optimize the entire circuits at cryogenic temperatures. This article presents a 144-Kb embedded dynamic random access memory (eDRAM)-based cryogenic IMC accelerator (eCIMC), supporting energy-efficient operations in different modes, including the conventional memory operation, the Boolean operation, and the convolutional operation. First, we optimize the cryogenic three-transistor (C3T) eDRAM bitcell to support multi-mode operations with high retention time. Second, we design an adaptive and reconfigurable sense amplifier (ARSA) to efficiently process both memory and Boolean operations by taking advantage of the C3T to store the reference voltage. Third, we present a 4-bit flash analog-to-digital converter (ADC) with 15 ARSAs and a four-cycle reference voltage generation scheme to achieve fast and low-power cryogenic convolutions. Measurement results of our test-chip show that the eCIMC achieves an average energy efficiency of 603.1 TOPS/W (4b $\times$ 4b) and a computing density of 284 TOPS/mm $^2$ (4b $\times$ 4b). Moreover, the retention time of our eCIMC has been significantly improved to 9.1 s at 4.2 K.