功率(物理)
计算机科学
计算机硬件
嵌入式系统
电气工程
物理
工程类
量子力学
作者
Hyun-A Ahn,Yoo‐Chang Sung,Yonghun Kim,Janghoo Kim,Kihan Kim,Dong Hoon Lee,Young-Gil Go,Jae Wook Lee,Jae-Woo Jung,Yong‐Hyun Kim,Garam Choi,J.-H. Park,B.H. Lee,Jin-Hyeok Baek,Dae‐Sik Moon,Ji Hyoun Lim,Dokshin Lim,Seung-Jun Bae,Tae-Young Oh
出处
期刊:IEEE Journal of Solid-state Circuits
[Institute of Electrical and Electronics Engineers]
日期:2024-01-01
卷期号:: 1-9
标识
DOI:10.1109/jssc.2024.3396615
摘要
For low-power 8.5-Gbps operation, 4th-generation 10-nm 16-Gb LPDDR5x DRAM I/O circuits and control methods are proposed in this article. The proposed I/O improves signal integrity (SI) and power integrity (PI) by using a self-pre-emphasized stacked driver in transmitter (Tx), a supply voltage insensitive data receiver (Rx), and an optimized clock tree in write clock (WCK) clock paths. The measured eye widths of Tx and Rx, which are the indicators of the SI/PI, are 0.66 unit interval (UI) and 0.57 UI at 8.5 Gbps, respectively. Also, the measured power consumption is reduced by 20.0% compared to the previous LPDDR5 SDRAM product.
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