数据保留
热离子发射
闪光灯(摄影)
电子
与非门
闪存
西格玛
物理
计算物理学
电荷(物理)
材料科学
光电子学
拓扑(电路)
电气工程
计算机科学
算法
逻辑门
核物理学
计算机硬件
工程类
粒子物理学
光学
量子力学
作者
Rashmi Saikia,Aseer Ansari,S. Mahapatra
标识
DOI:10.1109/irps48203.2023.10118096
摘要
Charge loss mechanisms during Data retention (DR) in GAA 3D NAND devices, Inter-cell charge loss of electrons in the Charge Trap Layer (CTL), and In-cell charge loss of electrons from tunnel oxide are modeled and analyzed using a physics-based Activated Barrier Double Well Thermionic Emission (ABDWT) model. The measured data retention characteristics for Solid Pattern (SP), of various distribution, sigma $(\sigma)$ of the lower tail of the Cell Voltage Distribution (CVD) has been studied and modeled for various temperatures and programming levels (PL). Checkered pattern (CP) measured long-term data retention characteristics at various temperatures and program levels are modeled for both the loss components. 10 years projection is extrapolated across temperature and programing levels.
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