Improved reversed nested miller frequency compensation techniques using flipped and folded flipped voltage follower with resistor for three stage amplifier

This paper presents three circuits to improve frequency compensation in three stage amplifier for large capacitive load of 100 pF. The first proposed circuit introduces Flipped Voltage Follower (FVF) in inner loop of Reversed Nested Miller Compensation (RNMC) to combat RHP zero whereas both second and third proposed circuits employ A Folded Flipped Voltage Follower (FFVF). The third proposed circuit uses an additional resistor in the outer compensation loop for double pole-zero cancellation. Further feed forward path has been used in all proposed circuits to improve the large signal response. The functionality is verified using TSMC 0.18 µm CMOS technology parameters in Tanner tool. The simulation results show maximum gain-bandwidth product (GBW) of 30 MHz, minimum phase margin (PM) of 60° and slew rate (SR) of 10 V/µS, and minimum common mode rejection ratio (CMRR) of 37.2 dB at unity gain frequency. The input-referred noise of the proposed circuits varies from 16.6 nV/Hz to 18.2 nV/Hzat unity gain frequency. Corner analysis is also included to show the robustness of the circuits.