A FPGA based implementation of Sobel edge detection

This paper presents an architecture for Sobel edge detection on Field Programmable Gate Array (FPGA) board, which is inexpensive in terms of computation. Hardware implementation of the Sobel edge detection algorithm is chosen because hardware presents a good scope of parallelism over software. On the other hand, Sobel edge detection can work with less deterioration in high level of noise. A compact study is also been done based on the previous methods. The proposed architecture uses less number of logic gates with respect to previous method. Space complexity is also reduced using proposed architecture.