Power analysis and design of wide dynamic range CMOS imaging sensors

Wide dynamic range (WDR) CMOS imaging sensors (CIS) are being designed for new portable, implantable and sensory applications, which demand low power consumption. Compared to normal CISs, high quality WDR CISs generally consume much more power. Up to now, the power consumption of a WDR CIS has never been formally studied. This paper focuses to model and analyze the power consumption of two major WDR CIS designs. Analytical equations are derived for the WDR CIS power, and are verified with HSPICE simulations. The analysis indicates that the power consumption of WDR CISs is dominated by the column bus driving power for large imaging array, while photocurrent related power is negligible. Hence, the WDR CIS power is heavily dependent on the load of the column bus and the read-out frequency. A new partial quantization scheme is developed to acquire WDR images with greatly reduced read-out frequencies. Its power consumption is also analytically derived and verified with HSPICE simulations. A 256×256 partial quantization column consumes about 124.0 nW/pixel in the 0.35μm CMOS process for 16-bit dynamic range and 30 Hz frame rate. The power analysis is further verified by experimental measurements of a proof-of-concept 32×32 partial quantization imaging sensor in the 0.35μm CMOS process.