A Highly Linear Multi-Clock Combining Phase Interpolator Insensitive to Interpolation Error

A novel highly linear phase interpolator (PI) is proposed to effectively reduce the quantization error in a frac-N PLL without calibration. The multiple clock phases from a conventional PI are combined to generate one output clock phase with greatly reduced interpolation error. The multiple clocks advance or retreat by one VCO period while staying in a circular order and are subsequently combined to realize the desired fractional phases. A prototype 1/8 PI is designed. Simulations show that, with a +/-2pS initial interpolation error and VCO frequency of 5GHz, the proposed linear PI can reduce the quantization noise level by >16dB at both close-in and far-out frequency offsets. As comparison, under the same condition, a conventional PI worsens quantization noise at close-in frequency offset than that without PI.