A Low-Jitter and Low-Fractional-Spur Ring-DCO-Based Fractional-N Digital PLL Using a DTC’s Second-/Third-Order Nonlinearity Cancellation and a Probability-Density-Shaping ΔΣM

This work presents a low-jitter and low-spur, fractional- $N$ ring-oscillator-based digital phase-locked loop (RO-DPLL). First, to suppress fractional spurs, the probability-density-shaping delta–sigma modulator (PDS- $\Delta \Sigma \text{M}$ ) is presented. Since the output codes of the PDS- $\Delta \Sigma \text{M}$ are designed to have a time-invariant probability density function (PDF), they have spur immunity to any nonlinearity (NL) of the digital-to-time converter (DTC). In addition, by using a special dither consisting of uniform random numbers (URNs) based on the dithered quantization theorems, the PDS- $\Delta \Sigma \text{M}$ can also suppress fractional spurs due to the NL of other loop-building circuits. Second, the DTC’s second-/third-order nonlinearity cancellation (DST-NLC) technique is presented to reduce the quantization noise (Q-noise), thereby reducing the rms jitter. The proposed RO-DPLL was fabricated in 65-nm CMOS, and it used a 0.146-mm ² silicon area and 9.27-mW power. At a near-integer- $N$ frequency, i.e., near 5.3 GHz, the measured rms jitter and the fractional spur were less than 365 fs and −63 dBc, respectively.