中间层
球栅阵列
互连
可靠性(半导体)
芯片级封装
电子包装
包装工程
材料科学
可靠性工程
炸薯条
机械工程
电子工程
计算机科学
工程类
焊接
电气工程
复合材料
图层(电子)
电信
功率(物理)
物理
蚀刻(微加工)
量子力学
作者
Hakjun Kim,Jae Young Hwang,Sarah Eunkyung Kim,Young‐Chang Joo,Hyejin Jang
出处
期刊:IEEE Transactions on Components, Packaging and Manufacturing Technology
[Institute of Electrical and Electronics Engineers]
日期:2023-09-20
卷期号:13 (10): 1624-1641
被引量:4
标识
DOI:10.1109/tcpmt.2023.3317383
摘要
Advanced packaging technology, also known as system scaling, bridges the gap between chip and package sizes by mounting multiple chips on a single package substrate. 2.5-D packaging utilizing a passive device has been widely adopted and showed enhanced capacity and performance. However, 2.5-D packaging presents its own challenges related to thermomechanical reliability because of the large size of the silicon interposer. This article reviews academic and industrial efforts to address the thermomechanical challenges associated with 2.5-D packaging, particularly silicon interposers, focusing on the warpage and board-level interconnect reliability. The topics include simulation and measurement methods to evaluate and predict the thermomechanical characteristics of package components, such as warpage and strain distribution, as well as fatigue and lifetime of ball grid arrays. The impacts of materials and geometrical design factors are also discussed. Finally, challenges of current approaches and outlooks are presented.
科研通智能强力驱动
Strongly Powered by AbleSci AI