平面布置图
可靠性工程
计算机科学
集成电路设计
芯片上的系统
嵌入式系统
工程类
作者
Nitesh Trivedi,Brett Carn,Aditya Poal
标识
DOI:10.23919/eos/esd54763.2022.9928484
摘要
Flawless design planning for ESD protection on large SoCs which needs to be intercepted during the floorplan stage of the SoC design cycle is getting important. Shortfall to integrate any essential protection and detecting such flaws during ESD signoff verification at a later stage of the SoC design cycle could lead to impactful last-minute SoC floorplan change, resulting in product time-to-market delays
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