SI/PI Co-Simulation Analysis of High-Speed I/O Link

The signal integrity (SI), power integrity (PI), and electromagnetic interference (EMI) issues have always been challenges faced by designers involved in three-dimensional (3D) packaged heterogeneous multi-chip modules or 3D integrated circuits, especially in the designing and validation of their high-speed input/output (I/O) links. Previously, most of these problems were usually analyzed separately. This paper proposes a SI/PI co-simulation analysis method and corresponding flow, based on a hybrid utilization of full-wave and lumped circuit simulation tool, for a more efficient co-analysis and accurate anticipation of the behavior of a 3D high-speed signal link and its corresponding power distribution network (PDN). Interaction among signal path reflection, crosstalk, PDN impedance and resonant along high-speed signal link are investigated and the mechanisms are summed up. Furthermore, example of a concise development frame for a complex miniaturized system, such as chiplet-based system-in-package, is demonstrated.