Atomistic Mechanism of 4 H - SiC/SiO2 Interface Carrier-Trapping Effects on Breakdown-Voltage Degradation in Power Devices

The $\mathrm{Si}\mathrm{C}/{\mathrm{Si}\mathrm{O}}_{2}$ interface in the termination area is a crucial component in limiting high-temperature reverse-bias (HTRB) reliability for $\mathrm{Si}\mathrm{C}$-based high-voltage devices. However, the atomic structure and carrier-trapping behavior of the $\mathrm{Si}\mathrm{C}/{\mathrm{Si}\mathrm{O}}_{2}$ interface defects therein and the underlying physical mechanisms of breakdown-voltage (${V}_{\mathrm{BD}}$) variation are still largely unclear. Here, the $\mathrm{Si}\mathrm{C}/{\mathrm{Si}\mathrm{O}}_{2}$ interface defects of 4H-$\mathrm{Si}\mathrm{C}$ gate turn-off (GTO) thyristors before and after HTRB stress are investigated by transient capacitance measurements and density-functional-theory (DFT) calculations. It is found that the bias stress at 4.4 kV enlarges the interface state density at ${E}_{C}\ensuremath{-}0.60$ eV to ${E}_{C}\ensuremath{-}1.33$ eV by electron capturing. As a result, the negative interface charge is generated. As high-resolution transmission electron microscopy reveals the presence of excess carbon near the $\mathrm{Si}\mathrm{C}$ surface, DFT calculations are focused on carbon-related interface defects to clarify the atomic and electronic structures of the $\mathrm{Si}\mathrm{C}/{\mathrm{Si}\mathrm{O}}_{2}$ interface trap and assign them to negatively charged excess split-interstitial carbon at the interface. Furthermore, technical computer-aided-design simulation further proves that the negatively charged $\mathrm{Si}\mathrm{C}/{\mathrm{Si}\mathrm{O}}_{2}$ interface defect is the main cause for the observed ${V}_{\mathrm{BD}}$ degradation after the HTRB test, which leads to a strong electric field crowding effect. These results not only provide deep physical insights underlying ${V}_{\mathrm{BD}}$ degradation in HTRB-stressed high-voltage devices, but are also of significant importance in the optimizations of device structure and oxidation technology for $\mathrm{Si}\mathrm{C}/{\mathrm{Si}\mathrm{O}}_{2}$ interfaces in high-voltage $\mathrm{Si}\mathrm{C}$ devices.