Design of a Paralleled SiC MOSFET Half-Bridge Unit With Distributed Arrangement of DC Capacitors

Discrete silicon carbide (SiC) mosfets are usually connected in parallel to increase their current carrying capacity. However, unequal switching losses and unequal transient current overshoot can limit the maximum switching frequency and maximum current carrying capacity of the paralleled unit. In this article, a paralleled half-bridge unit is proposed to improve the transient current sharing performance, which is characterized by a distributed arrangement of dc capacitors. First, the main causes of the transient current imbalance in traditional power layout are analyzed theoretically for the first time. Then, the traditional power layout is optimized by the ANSYSEM cosimulation techniques to improve the transient current sharing performance. The layout of the gate driver is also optimized to reduce the transmission delay of the gate drive signal. The double pulse tests are carried out to verify the current sharing performance under normal and short-circuit operating conditions. Compared with traditional power layout, the difference in a transient current overshoot of the low-side paralleled SiC mosfets is decreased significantly from 10.22% to 2.78% and the difference in switching losses is also reduced. A boost converter is constructed based on the paralleled half-bridge unit. A more uniform temperature distribution indicates the improved current sharing performance by optimizing the power layout.