System Model Evaluation of RISC-V Cores for improved performance and fault tolerance

As aerospace and defense firms are working towards developing future air and space platforms, decisions involving which hardware and software elements to use in their design need to be made. One significant design choice is the underlying Instruction Set Architecture (ISA) that defines the interface between the software and hardware for a processor. A relatively new ISA called RISC-V has emerged as an open-source alternative to commercial ISAs. Verifiable security, frozen base specification for long-term stability, designed for extensibility, and no license fee for modifications make RISC-V particularly well suited for aerospace and defense applications. It is important for the architect to evaluate not only the RISC-V core but the interaction of the core with other subsystems, data accesses, and interrupts. This has to be done in the scope of the target mission application at early design stages in order to minimize design bugs, reduce cost and optimize the design. In this work, we developed the system models of the RISC-V core and System-on-Chip (SoC) where the RISC-V cores were plugged in. Using the system model, we are able to run target applications/benchmarks on the RISC-V core and evaluate the performance and power for different clock frequencies, custom instructions, topology, cache associativity degrees, cache replacement policies, cache sizes, write-back policies, bus width, buffer sizes, bus speeds, memory types, and memory width. For each simulation, the system model generates various statistics including details on pipeline stalls, pipeline utilization, execution unit utilization, execution unit buffer occupancy, instruction and data cache accesses, cache hit ratio, number of evictions, writebacks, memory throughput, cycles per instruction, memory access latency and network latency. Using the system model, we were able to obtain debug logs from each SoC subsystem including the RISC-V cores. Using the pipeline traces for each instruction, we were able to verify the behavior of custom instructions which were introduced to improve our application performance. Performance and functional requirements were provided as input to the system model and faults were injected into the system model to determine the expected performance of the system under failure. Our SoC design was then updated to improve the fault tolerance and application performance by 4x times under faults by adding redundant cores and error correction mechanisms.