A 2 GHz bandwidth, 6-bit inverter-based open-loop amplifier for high-speed ADCs

This paper presents an inverter-based, open-loop amplifier for use in high-speed analog-to-digital converters. The proposed amplifier architecture utilizes bulk terminals for linearization and common-mode stabilization to minimize area overhead and power consumption. Post-layout simulated results show that the amplifier consumes 11.0 mW for an input frequency of 2 GHz. The resolution of the amplifier is limited by the gain variation. The presented amplifier achieves a resolution of 6 bits. The amplifier is designed to be part of a 4 GS/s pipeline ADC used in broadband systems.