A Noise-Canceling SMASH Architecture for Discrete-Time Bandpass Delta-Sigma ADCs

This paper presents a new architecture as well as a compensation method for discrete-time (DT) noise-canceling SMASH (NC-SMASH) bandpass delta-sigma modula-tors $(\mathbf{BP}-\Delta\Sigma \mathbf{Ms})$ . The proposed method relaxes timing constraints on the feedback path by one clock cycle, which in turn relaxes the timing constraints on the adder in front of the quantizer, and the digital adder for the SMASH architecture. In SMASH architectures, this relaxed timing enables an NC analog-to-digital converter (ADC) architecture. Unlike state-of-the-art solutions, which require an analog unit delay at the ADC's input to achieve these relaxed requirements, the presented bandpass approach renders this analog delay and the respective input capacitor unnecessary. In a respective circuit implementation this significantly reduces the area and power consumption. The proposed compensation method allows the designer to choose between a non-delayed input and an elimination of the input signal component inside the loop filter, which would require a delayed input path.