Through-silicon-via Architecture of 3D Integration for Superconducting Quantum Computing Application

As one of the mainstream technique routes to implement universal quantum computing, superconducting qubit has been highly anticipated in recent years. However, the current widely-using 2D interconnect forms are not capable to meet the interconnect demand of high integration quantum processor in practical use due to wiring congestion, electromagnetic crosstalk, mechanical stress concentration, limited interior space of dilution refrigerator, etc. Therefore, quantum packaging will also need to be updated from 2D planar to 3D vertical architecture for higher integration density of superconducting qubits. In view of the current chiplet development trends in IC industry, we propose a 3D integration architecture based on the partition strategy of qubit chiplet and bus chiplet for superconducting quantum computing. This chiplet solution respectively utilizes the TSV and microbump structure in superconducting constituent material scheme to achieve low-loss intra-layer and inter-layer connection, which provides a possible technical route for modular large-scale quantum processor. To verify the feasibility of the above architecture, we design a kind of TiN-based TSV test vehicle including daisy chain structure to inspect the stabilization of DC resistance and transmission line structure for evaluation of DC/microwave signal transporting performance during the cool-down process. The TSVs in this test vehicle possess high aspect ratio (10:1, $30 \mu\mathrm{m}$ diameter) fabricated by DRIE, coating with ∼200nm TiN layer by ALD. Subsequently, Al/TiN planar wiring layer is patterned by secondary lithography and ICP process. Then morphology observation, R.T./cryogenic electrical tests are successively carried out to evaluate the performance of TSV test vehicle. SEM along with EDS reveal that the TiN coating is conformal and defect-free with nearly vertical sidewall profile. Electrical tests show that TSV structures possess satisfactory linear ohmic characteristics and a wide range of process uniformity and repeatability at R.T. Additionally, the DC resistance and S 21 loss amplitude both exhibit abrupt drop during the cooling process, indicating that certain degree of superconducting transition has probably occurred. Therefore, the TiN-based TSV interposer elaborated in this paper combined with indium-based flip-chip TCB methods provides the possibility to implement 3D quantum integration architecture based on chiplet design.