Blue Laser Diode Annealed Top-Gate Low Temperature Poly-Si TFTs With Low Resistance of Source/Drain From Deposited n+ Layer

In this letter, a high performance and large area feasible top-gate low-temperature polysilicon thin film transistor (LTPS TFT) technology is reported. The poly-Si active layer was formed by crystallizing the plasma enhanced chemical vapor deposited (PECVD) amorphous silicon (a-Si) film using the blue laser diode anneal (BLDA) technique. The low resistance of source-drain (S/D) regions were formed from a heavily-doped PECVD a-Si layer. The fabricated top-gate LTPS TFTs exhibit excellent electrical performances, with the carrier mobility more than 556.66 cm2/V-s and on/off-current ratio over $1.58\times 10^{7}$ . This proposed technology is expected to promote the manufacturing lines to the higher generations.