Generation and elimination of silicon pitting for 300 mm CMOS process technologies

The complementary metal oxide semiconductor (CMOS) process technology in a 300 mm wafer fab experienced wafer center yield loss. In-line wafer defect inspection revealed gross silicon pitting at the wafer center as the root cause of the yield loss. Affected dies showed pitting at the interfacial corner between the silicon substrate and the isolation oxide. The mechanism of silicon pitting involves creation of silicon microdefects during several high-temperature furnace anneal process steps (liner oxide and posthigh energy phosphorus implant anneals) because of local die and global wafer level thermally induced mechanical stress at the silicon substrate to isolation oxide interfacial corner. In addition, implant-induced silicon microdefects from a high energy (>2 MeV) phosphorus implant, extending to the silicon surface provide a further significant contribution to the silicon microdefect population. The overall microdefect population is further aggravated by Ostwald ripening during a subsequent thick silicon-oxide furnace growth process, resulting in sufficient corner silicon microstructure damage to enhance wet-etching during a subsequent wet-clean leading to gross silicon pitting. Silicon pitting is eliminated by lowering either the liner oxide or postimplant anneal temperatures or skipping the high energy phosphorus implant. Incorporating a reduced liner oxide anneal temperature into the CMOS process flow eliminated the wafer-level yield loss at the wafer center associated with gross silicon pitting defects.