Gate-tunable giant tunneling electroresistance in van der Waals ferroelectric tunneling junctions

Ferroelectric tunneling junctions (FTJs) have attracted great interest due to their potential applications in non-volatile memories and neurosynaptic computing. In this work, high performance FTJs constructed with graphene and two-dimensional (2D) layered ferroelectric CuInP2S6 (CIPS) with out-of-plane polarization have been demonstrated. These van der Waals (vdW) heterostructure tunneling devices show tunneling electroresistance (TER) up to 107. Furthermore, the FTJs exhibit noticeable gate tunability, for which the on-state tunneling current can increase by 100% by applying a 50 V gate voltage through the conventional 260-nm-thick SiO2 dielectric layer. Our demonstration of gate-tunable, giant tunneling electroresistance highlights its potential in energy-efficient non-volatile memories and computing-in-memory functions.