电容
缩放比例
寄生电容
逻辑门
金属浇口
可靠性(半导体)
电子工程
过程(计算)
材料科学
计算机科学
等效门电路
还原(数学)
鳍
和大门
光电子学
电气工程
工程类
数学
栅氧化层
晶体管
物理
电极
操作系统
量子力学
几何学
复合材料
功率(物理)
电压
作者
Andrew Greene,Huimei Zhou,Ruilong Xie,Chanro Park,Laertis Economikos,V. Chan,Kerem Akarvardar,Ruqiang Bao,Indira Seshadri,Rena M. Conti,Miaomiao Wang,M. Sankarapandian,J. Demarest,Juntao Li,Liying Jiang,Kai Zhao,Robert R. Robison,Takashi Ando,N. Cave,Andreas Knorr
出处
期刊:Symposium on VLSI Technology
日期:2019-06-01
卷期号:: T144-T145
被引量:5
标识
DOI:10.23919/vlsit.2019.8776493
摘要
In this paper, we present for the first time a "Gate-Cut-Last" integration scheme completed within the Replacement Metal Gate (RMG) module. This novel gate cut (CT) technique allows the scaling of gate extension length past the end fin which reduces parasitic capacitance, leakage and performance variation. In addition, we demonstrate that CT-in-RMG is a promising alternative integration process that can enable scaling for future logic technology nodes. Device, circuit and reliability results are shown to compare this novel CT-in-RMG process to the conventional gate cut method.
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