作者
Andrew Greene,Huimei Zhou,Ruilong Xie,Chanro Park,Laertis Economikos,V. Chan,K. Akarvardar,Ruqiang Bao,Indira Seshadri,Rena M. Conti,Miaomiao Wang,M. Sankarapandian,J. Demarest,Juntao Li,Liying Jiang,Kai Zhao,Robert R. Robison,Takashi Ando,N. Cave,Andreas Knorr,Dinesh Gupta,Sivananda Kanakasabapathy,Dechao Guo,Bala Haran,Veeraraghavan Basker,Huiming Bu
摘要
In this paper, we present for the first time a "Gate-Cut-Last" integration scheme completed within the Replacement Metal Gate (RMG) module. This novel gate cut (CT) technique allows the scaling of gate extension length past the end fin which reduces parasitic capacitance, leakage and performance variation. In addition, we demonstrate that CT-in-RMG is a promising alternative integration process that can enable scaling for future logic technology nodes. Device, circuit and reliability results are shown to compare this novel CT-in-RMG process to the conventional gate cut method.