A survey on mapping and scheduling techniques for 3D Network-on-chip

Network-on-chips (NoCs) have been widely employed in the design of multiprocessor system-on-chips (MPSoCs) as a scalable communication solution. NoCs enable communications between on-chip Intellectual Property (IP) cores to perform a task seamlessly collaborating among them. Mapping and Scheduling methodologies are key elements in assigning application tasks, allocating the tasks to the IPs, and organizing communication among them to achieve some specified objectives. The goal of this paper is to present detailed state-of-the-art research in the field of mapping and scheduling of applications on 3D NoC, classify the works based on several parameters, and provide some potential research directions.