An Efficient Implementation Approach to FFT Processor for Spectral Analysis

This paper presents an efficient hardware implementation approach to a variable-size fast Fourier transform processor for spectral analysis. Due to its capability to handle different frame sizes, it can be adapted in situations where operating parameters necessitate adhering to different standard requirements. A serial real-valued processor with a new data-flow graph is considered as it requires the least number of multipliers. By joint use of stage-specific optimization and multiplierless structure, the overall hardware efficiency of the proposed design is enhanced. Clock-gating is employed to enable the variable size processor operation along with power reduction. A fixed-point analysis of the proposed design is considered. The proposed novel multiplierless structure is based on shift-and-accumulation. This also includes the generation (and sharing) of partial products based on their symmetries. The proposed design offers low area and low power as compared to the state-of-the-art. It is demonstrated for spectral analysis of electroencephalogram signals for machine-learning-based epileptic seizure prediction on a field programmable gate array platform.