德拉姆
访问时间
静态随机存取存储器
计算机科学
功率消耗
数据保留
电子线路
随机存取存储器
延迟时间
嵌入式系统
通用存储器
功率(物理)
动态随机存取存储器
电容器
计算机硬件
半导体存储器
电气工程
工程类
内存刷新
内存控制器
电压
计算机存储器
物理
计算机安全
量子力学
作者
Prateek Asthana,Sangeeta Mangesh
标识
DOI:10.1109/icacci.2014.6968474
摘要
In this paper average power consumption and timing parameter i.e. read access time, write access time and retention time comparison of 3T1D DRAM is carried out. These analyses are carried out on 32nm scale. This DRAM cell is used in high performance embedded system. A technique is being used in the paper to improve average power consumption and read access time for 3T1D DRAM to make it more comparable to the SRAM 6T. A circuit to improve the average power consumption and the read access time of the 3T1D cell are analyzed. These circuits are analyzed on TANNER EDA. Circuits are designed on SEDIT and simulated on TSPICE.
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