Method to improve the throughput and retain the CD performance for DUV process

One of the major problems for DUV resists is linewidth change owing to Post Exposure Delay (PED) and PEB conditions. In this work, the influence of PED and PEB baking conditions have been investigated based on the measured linewidth, i.e., critical dimension (CD). Our previously established model has been employed to describe the linewidth for various resists and process conditions. Based on our analyzed results, the process flow of wafer can be modified to improve the throughput, and still retain the CD stability and resist profile control.