Applying dynamic voltage stressing to reduce early failure rate

In this paper, a /spl sim/2/spl times/ improvement on average was achieved in early life failure rate (ELFR) reduction by applying a dynamic voltage stress (DVS) test at the chip probing (CP) stage. In our study, the ELFR reduction percentage has improved by up to 60% or more with the implementation of delta I/sub sb/ concept as the screening specification. By using this methodology, test during burn-in (TDBI), pre-burn-in testing or on board screening may not be necessary and burn-in duration can be reduced (e.g. originally, we needed 24 hr, but were able to reduce it to 9 hr with zero burn-in failure rate). We used a 6-transistor SRAM for our study, but this method could also be applied to general logic products.