The Process Challenge and Optimization of Self-Aligned Contact Etch

The self-aligned contact (SAC) is a key process in developing the next generation ultra-large scale integrated (ULSI) devices because its advantage on providing an efficient reduction of active array areas, decreasing the transistor gate features, and alignment margin improvements in photolithography (1-2). With the transistor gate feature size continuously scaled down, pattern density and aspect ratios continuously increase, conversely. It requires a robust etch process to solve the multiple issues such as hard mask (HM) loss loading between different patterns (trench, hole, etc.), HM shoulder profile, sidewall profile control (3). In this work, we examined the impact of various technologies on the extremely high aspect ratio SAC etch process, including source pulsing, bias pulsing, synchronous pulsing and the atomic layer etch (ALE) methods. Results indicate the introduction of pulsing function could significantly reduce the nitride loss while avoid the contact open. The synchronous pulsing and ALE scheme shows its superior capability on improving the trade-off between HM loss and profile control. To further improve the process margin, we also introduced a novel HM shape engineering. Finally we achieved a manufacturable SAC process without any side effect. Acknowledgments The authors gratefully acknowledge support from Shanghai Sailing Program. References Kim, J. Vac. Sci. Technol. A 23 (4), 7(2005). Kim, J. Vac. Scl. Technol. B 20 (5), 9(2002) H. Zheng, A study of self-aligned contact etch of NOR flash , China Semiconductor Technology International Conference (2015).