A new method for preventing CMOS latch-up

We propose a near method for preventing CMOS latch-up. This method uses a high-energy (MeV), blanket (mask less), boron implant, which reduces the substrate resistance by creating a p-buried layer under the CMOS devices. Since this implant is performed after the n-well drive-in diffusion, the thickness of the lightly doped layer above the implant can be controlled better and scaled more easily. Furthermore, the p to p+ transition region is sharper and, therefore , the suppression of latch-up is more effective than the use of a p-type epilayer on a p+ substrate. Simulations confirm that the increase in holding and critical currents are due to a reduced substrate resistance.